Advanced VHDL Simulations and Testbenches

The need for a systematic approach towards verifying digital systems has given rise to advanced testbench verification methodologies such as OS-VVM, OVM, UVM and AVM. This course covers advanced functional simulation techniques using major VHDL-based verification frameworks (OS-VVM, UVVM), temporal assertions-based verification using the Property Specification Language (PSL), as well as interfacing a VHDL testbench with an external computer program (C or Perl) using the VHDL Procedural Interface (VHPI). These tools allow engineers to systematically and accurately validate designs with minimal test cases. Ultimately, this course aims to arm engineers with powerful tools to ensure their designs can be properly tested in a timely manner.