VHDL Simulations and Testbenches

The ubiquity and complexity of commercial, professional and industrial digital systems has been increasing exponentially over the years as we integrate more and more features into these systems. Coupled with the ever shortening time-to-market and the proliferation of systems in safety critical areas, the immense challenges of engineers are to ensure their complex designs are error free and conform to the desired functionality. These challenges has made verification, especially at the presilicon stage, a vital stage in the design process.

The need for a systematic approach towards verifying digital systems has given rise to advanced testbench verification methodologies such as OS-VVM, OVM, UVM and AVM. This course introduces the key testbench concepts and verification framework of OS-VVM, that allow engineers to systematically and accurately validate designs with minimal test cases. The course covers the simulation of digital systems and the design of proper testbenches for verification. Ultimately, this course aims to arm engineers with a powerful tool to ensure their designs can be properly tested in a timely manner.