Course Details

VHDL For Synthesis

Field Programmable Gate Arrays have allowed engineers to develop complex, sophisticated and extremely fast digital systems. Due to their versatility, they are also by far the most feasible option for prototyping. The complexity of digital systems however, meant it is more than necessary to develop such systems in hardware description languages (HDL) rather than schematic capture.

This course introduces the complete FPGA development flow and environment with VHDL. The emphasis here is on the subset of VHDL that is synthesizable — i.e. capable of producing hardware — rather than the entire HDL. Proper, generic hardware description style and implementation techniques are introduced throughout the course.