Course Details

Transaction-Level Modelling and Bus Functional Modelling

We introduce the concept of transaction-level modelling (TLM) and bus functional modelling (BFM) in this course, which are methods to encapsulate low-level signaling into high-level transactions. TLM/BFM simplify testbench and system-level designs by separating the low-level bus models from the higher-level transactor abstractions, making your testbenches/SoC designs easier to manage and maintain. These concepts are very important for testbench simulations as well as synthesizable SoC bus interface designs.

Participants will have an in-depth understanding of TLMs and BFMs, and will design transactors and bus functional models for a simple FIFO application, commonly found in numerous real-world applications. We demonstrate how modules could easily communicate with one another via a bus interface designed using TLM and BFM techniques. Communicating between two individual testbench/SoC components is as simple as making a procedure-call statement.